(a) Field of the Invention
The present invention relates to a driving device of a plasma display panel (PDP).
(b) Description of the Related Art
A PDP is a flat display for showing characters or images using plasma generated by gas discharge. PDPs can include pixels numbering more than several million in a matrix format, in which the number of pixels are determined by the size of the PDP. Referring to FIGS. 1 and 2, a PDP structure will now be described.
FIG. 1 shows a partial perspective view of the PDP, and FIG. 2 schematically shows an electrode arrangement of the PDP.
As shown in FIG. 1, the PDP includes glass substrates 1, 6 facing each other with a predetermined gap therebetween. Scan electrodes 4 and sustain electrodes 5 in pairs are formed in parallel on glass substrate 1. Scan electrodes 4 and sustain electrodes 5 are covered with dielectric layer 2 and protection film 3. A plurality of address electrodes 8 is formed on glass substrate 6, and address electrodes 8 are covered with insulator layer 7. Barrier ribs 9 are formed on insulator layer 7 between address electrodes 8, and phosphors 10 are formed on the surface of insulator layer 7 and between barrier ribs 9. Glass substrates 1, 6 are provided facing each other with discharge spaces between glass substrates 1, 6 so that scan electrodes 4 and sustain electrodes 5 can cross address electrodes 8. Discharge space 11 between an address electrode 8 and a crossing part of a pair of scan electrodes 4 and sustain electrodes 5 forms discharge cell 12, which is schematically indicated.
As shown in FIG. 2, the electrodes of the PDP have an n×m matrix format. Address electrodes A1 to Am are arranged in a column direction, and n scan electrodes Y1 to Yn and n sustain electrodes X1 to Xn are arranged in a row direction.
In general, a single frame is divided into a plurality of subfields in the PDP, and displayed images are represented by a combination of the subfields. As shown in FIG. 3, each subfield has a reset period, an address period, and a sustain period. In the reset period, wall charges formed by previous sustain-discharging are erased, and the wall charges are set up so that the next addressing can be stably performed. In the address period, cells that are turned on and those that are turned off are selected, and the wall charges are accumulated to the cells that are turned on (i.e., addressed cells). In the sustain period, sustain-discharging is executed so as to display the actual image on the addressed cells.
FIG. 3 shows a conventional PDP driving waveform. As shown, a reset period includes erase period (a), ramp rising period (b), and ramp falling period (c).
In erase period (a), an erase ramp waveform that gradually rises toward Ve volts (V) from 0V is applied to sustain electrode X. This way, the wall charges formed on sustain electrode X and scan electrode Y are gradually erased. As used herein, the wall charges refer to charges that accumulate to the electrodes and are formed proximately to the respective electrodes on the wall (e.g., dielectric layer) of the discharge cells. The wall charges do not actually touch the electrodes themselves, but they are described herein as being “formed on”, “stored on” and/or “accumulated to” the electrodes. Further, the wall voltage as used herein refers to a voltage potential that exists on the wall of discharge cells, which is caused by the wall charges.
In ramp rising period (b), address electrode A and sustain electrode X are maintained at 0V, and a ramp waveform that gradually rises toward Vset volts from Vs volts is applied to scan electrode Y. While the ramp waveform rises, a first fine resetting is generated to address electrode A and sustain electrode X from scan electrode Y in all the discharge cells. Accordingly, negative wall charges are stored on scan electrode Y, and positive charges are concurrently stored on address electrode A and sustain electrode X.
In ramp falling period (c), a ramp waveform that gradually falls toward 0V from Vs volts is applied to scan electrode Y while sustain electrode X is maintained at Ve volts. While the ramp waveform falls, a second fine resetting is generated to all the discharge cells. As a result, the negative wall charges of scan electrode Y reduce, and the positive wall charges of sustain electrode X reduce.
When the reset period operates normally, the wall charges of scan electrode Y and sustain electrode X are erased, but unstable discharging may occur because of unstable resetting. The unstable discharging includes a first case in which discharging caused by self-erasing occurs at the time when voltage of scan electrode Y falls to Vset after strong discharging during a ramp rising period, a second case in which strong discharging occurs in a ramp rising period and a ramp falling period, and a third case in which strong discharging occurs during a ramp falling period.
In the first case, a reset function is performed according to self-erasing. However, in the second and third cases, positive wall charges are generated on scan electrode Y and negative wall charges are generated on sustain electrode X because of strong discharging during the ramp falling period. In these instances, if wall voltage Vwxy1 caused by the wall charges formed on scan electrode Y and sustain electrode X satisfies Equation 1, sustain-discharging can be generated in the sustain period even when no addressing occurs in the address period.Vwxy1+Vs>Vf  Equation 1
where Vwxy1 is the wall voltage formed between scan electrode Y and sustain electrode X because of strong discharging in the ramp falling period; Vs is a voltage difference generated between scan electrode Y and sustain electrode X because of sustain pulses applied in the sustain period; and Vf is a discharge firing voltage between scan electrode Y and sustain electrode X.
Therefore, when the conventional driving method of FIG. 3 is used in a PDP, sustain-discharging can occur in the discharge cells that are not to be turned on because of strong discharging during the ramp falling period in the reset period.